SMD Test Points and Design-for-Test Guidelines for PCBAs

Every SMD test point on your board is a decision about what can be tested in production and what can't. Get the pad sizes, spacing, and placement wrong during layout, and the problems don't show up until someone tries to build a bed-of-nails fixture — at which point fixing them means a board respin.

This guide covers the design-for-test (DFT) guidelines that determine whether your PCBA can be probed reliably at scale. The specs here come from years of fixture builds across thousands of board designs.

Why DFT Matters#

The decisions you make during PCB layout determine the ceiling of your test coverage. Not the test plan. Not the fixture design. Your layout.

A board with properly sized and spaced test points can be probed with standard spring-loaded pins at high speeds. Every critical net gets verified. Faults get isolated to individual components. The fixture is straightforward to build.

A board without adequate test access forces compromises. The fixture designer either uses fine-pitch probes that wear faster and cost more, or marks nets as untestable. You end up with coverage gaps that only show up as field failures months later.

The specifics matter here. A test point that's 0.7mm instead of 1.0mm doesn't just reduce probe reliability slightly — it changes which probes can be used, which affects probe life, which affects per-board test cost across your entire production run. These details compound.

Test Point Types and Sizes#

A test point is any pad or via that provides probe access to a circuit net. But not all test points are equal — SMD pads, vias, and through-hole pads each have different sizing rules and probe compatibility.

SMD Pads#

The most common surface mount test point. Circular or square pads placed on the board surface specifically for probe contact.

Use the largest pads your layout allows. Bigger pads mean more reliable probe contact, which means fewer false failures during testing. A test that intermittently fails because the probe can't make clean contact wastes everyone's time.

Vias as Test Points#

Vias can double as test points if they meet two conditions: they're not tented (covered with solder mask), and the hole is small enough for the probe to make contact.

If the via hole is larger than 0.5mm, the probe tip may fall into the hole instead of contacting the annular ring. You'd need a probe with a larger head diameter — which means wider spacing requirements and potentially a more expensive fixture. When using vias for test access, specify them as untented in your Gerber output.

Through-Hole Pads#

Through-hole component pads provide natural test access, but the probe selection depends on whether the component is populated.

This distinction matters. Using the wrong probe style on a through-hole pad means unreliable contact at best, and damaged components at worst.

Spacing Requirements#

Probe spacing determines whether the fixture plate can physically accommodate all the pins needed to test your board. Too tight and the probes interfere with each other — or the fixture can't be manufactured at all.

The center-to-center minimum of 1.27mm corresponds to a P50 probe pitch — the finest standard probe size. These probes are more expensive, wear faster, and require tighter manufacturing tolerances on the fixture plate. At 1.9mm (P75 pitch), you're in the sweet spot: standard probes, reasonable fixture cost, reliable contact.

Placement Rules#

Single-side access. Place all test points on one side of the board. Dual-side probing doubles the fixture complexity — you need two probe plates, two sets of alignment hardware, and the board must be compressed from both sides simultaneously. It's possible, but it adds significant cost and reduces throughput.

Even distribution. Spread test points across the board surface rather than clustering them. Areas of high probe density cause the PCB to flex during testing, which affects measurement reliability and can damage fine-pitch components. If a dense area is unavoidable, plan for additional pressure pins in that region.

Keep-out zones. Maintain clearance from board edges and tall components. A test point in the shadow of a tall capacitor or connector can't be reached by a straight probe — and angled probing adds cost and reduces reliability. As a rule of thumb for height clearance: components under 5mm tall need 2mm clearance from the nearest test point, 5–10mm tall need 3mm, and anything over 10mm needs clearance of roughly height × 0.3.

Priority Nets#

Not every net needs a test point — but some nets are non-negotiable. When board area forces you to prioritize, allocate test points in this order:

1. Power rails and ground — every supply voltage and ground reference needs a test point. Without them, the fixture can't verify the most basic requirement: that the board has power. Ground test points also serve as measurement references for all other probes.
2. Critical signals — clocks, resets, enables, and any signal whose failure disables entire subsystems. A stuck reset line takes down the whole board; catching it requires probe access.
3. IC connections — BGA breakout traces and QFN thermal pads that are otherwise inaccessible after assembly. These are the nets most likely to have solder defects and least likely to be caught without dedicated test access.
4. Passive component networks — resistor dividers, filter capacitors, and termination networks. Lower priority individually, but in aggregate they represent a large fraction of assembly defects.

On a simple board this ordering is academic — you have room for test points on everything. On a dense design with 200+ nets competing for board area, it determines which defects your fixture catches and which slip through to functional test or the field.

Panel Layout Considerations#

When boards are panelized for assembly, test point placement needs to account for the panel structure. Test points near panel break tabs may be inaccessible to probes — the tab material extends beyond the board edge and can interfere with the fixture plate. They may also be damaged during depaneling, especially with routed or V-scored panel edges.

Position test points at least 5mm from any panel break tab. Also verify that your panel tooling holes are compatible with your fixture alignment strategy — panel-level tooling holes and board-level tooling holes serve different purposes, and the fixture needs to reference one set consistently.

Component Selection for Testability#

Some component packages make testing straightforward. Others make it difficult or impossible without workarounds.

Leaded packages (SOIC, QFP, through-hole) provide natural test access. The pins themselves can be probed, or the traces connecting to them can carry dedicated test points. Standard footprints have established probing strategies.

Ball Grid Arrays (BGAs) are the most common testability challenge. The solder balls are underneath the package — no probe can reach them after assembly. Every BGA net that needs testing requires either a dedicated test point on a breakout trace or boundary scan access through JTAG.

QFN/DFN packages have a similar problem. The thermal pad and ground connections are on the bottom of the package. After assembly, those pads are inaccessible. Include test points on the traces connected to critical QFN pins.

Fine-pitch passives (0201 and smaller) can technically be probed on their pads, but it's unreliable at production speeds. The pads are too small for consistent spring-probe contact. Provide dedicated test points on the connected nets instead.

Mitigation Strategies#

For packages without direct probe access:

1. Add test points on connected nets — probe the trace, not the component
2. Use boundary scan — test digital connections through JTAG without physical probing
3. Design for functional test — structure the circuit so that component faults produce measurable behavioral changes
4. Accept reduced coverage — document which components rely on functional verification only

There's a tradeoff here. Every test point takes board area. On a dense design, you may not have room for test points on every BGA breakout net. The decision about which nets get test access and which don't should be made during design review, not discovered during fixture development.

Boundary Scan (JTAG) Considerations#

Boundary scan provides test access to digital connections without physical probing. It's not a replacement for bed-of-nails testing — it complements it by reaching nets that probes can't.

When to Include JTAG#

• Multiple BGAs with interconnected data buses
• High-pin-count processors where breakout test points don't fit
• Board density that prevents adequate test point placement on digital nets
• Production volumes that justify the JTAG infrastructure investment

Design Requirements#

• Include a JTAG connector with standard pinout (IEEE 1149.1)
• Maintain chain integrity — a broken JTAG chain disables testing for all downstream devices
• Add pull-up and pull-down resistors per device datasheet requirements
• Verify all devices in the chain support boundary scan

Boundary scan handles digital interconnect verification well. It doesn't test analog circuits, power supply integrity, or passive component values — those still need physical probe access. For a deeper look at how in-circuit testing and boundary scan work together, see in-circuit testing.

Test Coverage Targets#

Coverage targets aren't arbitrary quality numbers. They're business decisions that directly affect how many test points your board needs, which determines fixture complexity and cost.

Coverage below 80% usually indicates significant DFT gaps — not a deliberate decision, but a sign that test access wasn't part of the design process. At that level, you're missing defects that only surface in the field.

Test Point Count Guidelines#

Coverage targets translate to concrete test point counts. The right number depends on board complexity and your target coverage:

These ranges assume single-side probing with standard P75 (1.9mm) probe pitch. Tighter pitch (P50) allows more test points per square centimeter but at higher fixture cost. If your count exceeds what your board area can accommodate at your target pitch, that's a signal to incorporate boundary scan for digital nets and accept functional-test-only coverage on lower-priority analog nets.

Board Alignment and Mechanical Requirements#

These are the DFT details that PCB designers most often miss, because they're fixture-side concerns that don't show up in EDA design rule checks. But they directly affect whether a fixture can be built for your board — and how much it costs.

Tooling Holes#

Tooling holes are how the fixture aligns your board. Without them, the fixture builder has to cradle the board by its outline — a custom machined part that adds cost and reduces alignment accuracy.

• Quantity: 2 or more
• Diameter: >2mm
• Placement: Opposite corners of the PCB

Two tooling holes in diagonal corners give the fixture two-point alignment. Adding a third creates redundancy and improves positional accuracy for large boards.

Mounting Holes#

Mounting holes can double as fixture alignment points using spring guide pins. The pin diameters depend on the hole size:

Recommend 3–4 mounting holes for reliable alignment. If your board already has mounting holes for the enclosure, they can serve both purposes — no additional board area needed.

Pressure Pins#

Pressure pins push down on the top side of the board to hold it firmly against the probe plate during testing. Without enough pressure, the board lifts or flexes and probes lose contact.

• Minimum quantity: 5 pins, increasing with board size and test point count
• Tip diameter: 2.5mm
• Clearance from tall components: 3.175mm (125 mil)
• Placement: Top side of board only

You need to leave space for pressure pins in your layout. If the top side is covered edge-to-edge with tall components, there's nowhere for the pins to press. This is especially common on boards where designers maximize component density without considering mechanical test access.

How DFT Decisions Affect Your Fixture#

Every DFT decision in your layout maps to a physical consequence in the test fixture.

Pad size determines probe selection. A 1.0mm SMD pad can be probed with a standard crown-tip probe — reliable, inexpensive, long-wearing. Drop to 0.7mm and you need a fine-tip probe with less contact surface, shorter life, and higher per-unit cost.

Spacing determines fixture plate density. At 1.9mm pitch, the fixture plate uses standard drill patterns. At 1.27mm, the fixture builder needs tighter tolerances and thicker plates to prevent probe-to-probe interference.

Single-side vs. dual-side determines fixture count. One probe side means one fixture plate. Test points on both sides means two plates, two alignment systems, and a compression mechanism that holds the board between them. The fixture cost roughly doubles — and test throughput drops because setup takes longer.

Missing tooling holes force a custom cradle. Instead of simple alignment pins, the fixture builder machines a cradle that captures the board outline. It's an additional custom part that adds cost and lead time.

Insufficient pressure pin space means flex. If the board can't be held flat against the probes, contact pressure varies across the surface. Some probes make solid contact. Others don't. The result is intermittent test failures that waste production time.

When you're making DFT tradeoffs during layout — balancing board density against test access — these are the downstream costs you're accepting or avoiding. For more on fixture types and how they work, see bed-of-nails test fixtures.

Common DFT Mistakes#

These are the issues that come up repeatedly during fixture development. Every one of them is cheaper to fix during layout than after.

1. Test points added as an afterthought. Pads squeezed into leftover space after routing, instead of placed where they're needed for coverage.
2. Insufficient spacing. Test points at 1.0mm pitch that can't be probed with any standard pin. The fixture either uses custom probes or those nets go untested.
3. No access on power rails. Power and ground nets need test points for supply verification and measurement reference. They're frequently overlooked.
4. Dual-sided access when single-sided is possible. Putting test points on both sides without checking whether a single-side layout would work.
5. Test points under tall components. A pad in the shadow of a 15mm connector is inaccessible to a straight probe.
6. No tooling holes. Forces a custom alignment cradle, adding cost and reducing positional accuracy.
7. Tented vias intended for test access. The solder mask covers the pad surface. Specify untented vias in the Gerber output for any via that will be probed.
8. No pressure pin clearance. The entire top surface is populated with components, leaving no room for the pins that hold the board against the probe plate.
9. Test points near panel break tabs. Pads within 5mm of a V-score or routed tab get damaged during depaneling or blocked by tab material during probing.

DFT Checklist#

Use this during design review before finalizing your layout:

Test Points:

• All critical nets have dedicated test points
• SMD test pads meet size requirements (≥0.8mm, preferably ≥1.0mm)
• Test point spacing meets requirements (≥1.27mm, preferably ≥1.9mm)
• Test points on one side of the board
• Edge and component keep-out zones respected
• Vias intended for test access are untented

Components:

• BGA connections have test points on breakout traces
• QFN/DFN critical nets have dedicated test points
• Boundary scan included if needed
• Programming access available (JTAG header or test points on programming signals)

Mechanical:

• At least 2 tooling holes (>2mm, opposite corners)
• 3–4 mounting holes for alignment
• Space reserved for pressure pins on top side
• Pressure pin clearance from tall components (≥3.175mm)

Analysis:

• Test coverage calculated against target
• Coverage meets target for your application
• Fixture feasibility reviewed with test team

Frequently Asked Questions#

What size should SMD test points be?#

Preferred pad diameter is 1.0mm (40 mil) or larger. The absolute minimum for reliable probing is 0.8mm (32 mil). Larger pads mean more consistent probe contact and fewer false test failures in production.

What is the minimum spacing between test points?#

1.27mm (50 mil) center-to-center at absolute minimum, which requires P50 fine-pitch probes. The preferred spacing is 1.9mm (75 mil), which allows standard P75 probes — less expensive, longer-wearing, and more reliable.

Can vias be used as test points?#

Yes, if two conditions are met: the via is not tented (no solder mask over the pad), and the hole diameter is 0.5mm (20 mil) or smaller. Larger holes risk the probe tip falling in rather than contacting the annular ring.

Do I need test points on both sides of the board?#

Avoid it if possible. Single-side probing keeps the fixture simple and affordable. Dual-side probing approximately doubles fixture cost and complexity. Only go dual-side when the layout genuinely requires test access on both surfaces.

How does DFT affect fixture cost?#

Directly. Larger pads and wider spacing use cheaper, more reliable probes. Single-side access means one fixture plate instead of two. Tooling holes eliminate the need for custom alignment cradles. Every DFT shortcut you take during layout becomes a cost that the fixture absorbs.

Next Steps#

You've got the guidelines. Now check whether your current design follows them.

For a broader view of PCBA testing approaches beyond DFT, see how to test circuit boards. If you're working in Altium Designer, see exporting test point reports for the EDA-specific workflow.